1. Field of the Invention
The present invention provides a method of making high voltage metal oxide semiconductor (HVMOS) devices and submicron metal oxide semiconductor (Submicron MOS) devices, and more particularity a method of integrating HVMOS devices and Submicron MOS devices with a shallow trench technology.
2. Description of the Prior Art
With the rapid growth of the integrated circuit (IC) market and the desire for highly integrated IC products, how to integrate HVMOS devices and Submicron MOS devices, and how to simultaneously form a large number of both HVMOS devices and Submicron MOS devices on a silicon wafer are important issues at the present time.
Please refer to FIG. 1. FIG. 1 is a cross-sectional diagram of an HVMOS device 30 formed on a silicon substrate according to the prior art method. As shown in FIG. 1, the HVMOS device 30 is formed on a silicon substrate 10. A shallow trench process is performed first to form a plurality of shallow trenches 12,14 and to define at least one active region 16 isolated by the shallow trenches 12, 14 on the silicon substrate 10. Then, two not adjacent field oxide (FOX) layers 18,20 are formed on a surface of the active region 16. After that, a gate 22 is formed on the surface of the active region 16 between the two not adjacent field oxide layers 18,20, and a portion of the gate 22 covers the field oxide layers 18,20. A first ion implantation processes is thereafter performed to form two first ion implantation regions 24,26 on the surface of the active region 16 not covered by the gate 22 and the field oxide layers 18,20. A second ion implantation process is then performed to form two second ion implantation regions 28,32 underneath the field oxide layers 18,20. The first ion implantation regions 24,26, being used as double diffused drains (DDD), are taken as a source and a drain of the HVMOS device 30. The second ion implantation regions 28,32 are used as drift regions of the HVMOS device 30.
However, smaller feature size in integrated circuits is always a dominant factor in driving technology progress. As the feature size becomes small, the drift regions 28,32 of the HVMOS device 30 underneath the field oxide layers 18,20 become an issue since the internal stress generated by the field oxide layers 18, 20 and the bird beak encroaching the field oxide layers 18, 20 limit the minimum feature sizes of the drift regions 28,32 of the HVMOS device 30.
Please refer to FIG. 2. FIG. 2 is a cross-sectional diagram of an HVMOS device 52 and a Submicron device 56 formed on a silicon substrate according to the prior art method. The HVMOS device 52 and the submicron MOS device 56 are formed on a silicon substrate 40. A shallow trench process is performed first to form a plurality of shallow trenches 42, 44, 46 on the silicon substrate 40. At the same time, at least one active region 48 of the HVMOS device 52 and at least one active region 54 of the Submicron MOS device 56, isolated by shallow trenches 42, 44, 46, are defined on the silicon substrate 40. After that, two not adjacent field oxide layers 58,62 of the HVMOS device 52 are formed on the surface of the active region 48. A thick gate oxide layer (not shown) is thereafter formed on the surface of the silicon substrate 40. Next, portions of the thick gate oxide layer (not shown) not defined as a thick gate oxide region 64 of the HVMOS device 52 is etched and removed to form the thick gate oxide region 64 of the HVMOS device 52.
Because the thick gate oxide layer (not shown) and the shallow trenches 42,44,46 are all made of silicon oxide, divots 66, 68 are formed near the top corner of the shallow trenches 44,46 around the Submicron MOS device 56, when an etching process is performed to the thick gate oxide layer (not shown) of the HVMOS device 52. The divots 66, 68 result in a kink effect that reduces the threshold voltage. In addition, polysilicon may fill in the divots 66, 68 in the subsequent poly gate process to generate a leakage current. It is thus difficult to integrate both HVMOS devices and Submicron MOS devices having small feature sizes on a silicon wafer.
Therefore, it is very important to develop a method of integrating HVMOS devices and Submicron MOS devices having small features on the silicon wafer to avoid the kink effect.